[bootlin/training-materials updates] master: kernel: iomem: Reword the ordering slide (6f73ae63)

[Miquel Raynal]

Repository : https://github.com/bootlin/training-materials
On branch  : master
Link       : https://github.com/bootlin/training-materials/commit/6f73ae6336771586bd92d2723b59c53ccfb0ece2

>---------------------------------------------------------------

commit 6f73ae6336771586bd92d2723b59c53ccfb0ece2
Author: Miquel Raynal <miquel.raynal at bootlin.com>
Date:   Thu Jun 2 17:30:30 2022 +0200

    kernel: iomem: Reword the ordering slide
    
    Re-use the previous sentences.
    Drop the "issuing" wording.
    Focus on the real guarantees of barries: ordering (rather than how this
    is usually achieved).
    
    Signed-off-by: Miquel Raynal <miquel.raynal at bootlin.com>


>---------------------------------------------------------------

6f73ae6336771586bd92d2723b59c53ccfb0ece2
 .../kernel-driver-development-io-memory.tex                | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/slides/kernel-driver-development-io-memory/kernel-driver-development-io-memory.tex b/slides/kernel-driver-development-io-memory/kernel-driver-development-io-memory.tex
index 3632d120..7f197ccb 100644
--- a/slides/kernel-driver-development-io-memory/kernel-driver-development-io-memory.tex
+++ b/slides/kernel-driver-development-io-memory/kernel-driver-development-io-memory.tex
@@ -177,10 +177,16 @@ void write[bwlq](unsigned val, void *addr);
 \begin{frame}[fragile]
   \frametitle{Ordering}
   \begin{itemize}
-  \item \code{write[bwlq]} ensures all prior writes have been posted
-  \item \code{read[bwlq]} ensures the read has been issued before continuing
-  \item Reordering is prevented to avoid trouble if the device expects
-    one register to be read/written before another one!
+  \item The compiler and/or CPU can reorder memory accesses, which
+    might cause trouble for your devices is they expect one register
+    to be read/written before another one.
+    \begin{itemize}
+    \item Memory barriers are available to prevent this reordering
+    \item \code{write[bwlq]} starts with a write memory barrier which
+      prior writes cannot cross
+    \item \code{read[bwlq]} ends with a read memory barrier which
+      guarantees the ordering with regard to the subsequent reads
+    \end{itemize}
   \item Sometimes compiler/CPU reordering is not an issue, in this case
     the code may be optimized by dropping the memory barriers, using the
     relaxed helpers: