[bootlin/training-materials updates] master: kernel: serial: better explanation of the last init operations (1ea0fd73)

[Miquel Raynal]

Repository : https://github.com/bootlin/training-materials
On branch  : master
Link       : https://github.com/bootlin/training-materials/commit/1ea0fd7393d16ac5dcd0f67b80d8a7d87b09e735

>---------------------------------------------------------------

commit 1ea0fd7393d16ac5dcd0f67b80d8a7d87b09e735
Author: Miquel Raynal <miquel.raynal at bootlin.com>
Date:   Tue Aug 3 10:48:40 2021 +0200

    kernel: serial: better explanation of the last init operations
    
    Writing 0x00 to MDR1 is actually part of the "change the clock" operation:
    1/ The value 0x7 is written to the MDR1 register, meaning: the hardware
       block is disabled
    2/ The baud divisors and various PLLs are initialized
    3/ Tje MDR1 register is set to 0x0, meaning: let's use the UART (instead
       of IRDA).
    
    So move this line to stick to the block initializing the baud rate.
    
    Also update the comment because the next line does not reset anything,
    but just clears the FIFOs and FIFOs counters.
    
    Signed-off-by: Miquel Raynal <miquel.raynal at bootlin.com>


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1ea0fd7393d16ac5dcd0f67b80d8a7d87b09e735
 labs/kernel-serial-iomem/kernel-serial-iomem.tex | 2 +-
 labs/kernel-serial-iomem/uart-line-init.c        | 1 +
 labs/kernel-serial-iomem/uart-line-reset.c       | 3 +--
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/labs/kernel-serial-iomem/kernel-serial-iomem.tex b/labs/kernel-serial-iomem/kernel-serial-iomem.tex
index 83d80e50..b37bf1a2 100644
--- a/labs/kernel-serial-iomem/kernel-serial-iomem.tex
+++ b/labs/kernel-serial-iomem/kernel-serial-iomem.tex
@@ -200,7 +200,7 @@ Declare \code{baud_divisor} and \code{uartclk} as \code{unsigned int}.
 
 \subsection{Soft reset}
 
-The last thing to do is to request a software reset:
+The last thing to do is to reset the FIFOs:
 
 \sourcecode{labs/kernel-serial-iomem/uart-line-reset.c}
 
diff --git a/labs/kernel-serial-iomem/uart-line-init.c b/labs/kernel-serial-iomem/uart-line-init.c
index 85710975..dcd8afdd 100644
--- a/labs/kernel-serial-iomem/uart-line-init.c
+++ b/labs/kernel-serial-iomem/uart-line-init.c
@@ -14,3 +14,4 @@ reg_write(serial, UART_LCR_DLAB, UART_LCR);
 reg_write(serial, baud_divisor & 0xff, UART_DLL);
 reg_write(serial, (baud_divisor >> 8) & 0xff, UART_DLM);
 reg_write(serial, UART_LCR_WLEN8, UART_LCR);
+reg_write(serial, 0x00, UART_OMAP_MDR1);
diff --git a/labs/kernel-serial-iomem/uart-line-reset.c b/labs/kernel-serial-iomem/uart-line-reset.c
index 93e025e6..2913f335 100644
--- a/labs/kernel-serial-iomem/uart-line-reset.c
+++ b/labs/kernel-serial-iomem/uart-line-reset.c
@@ -1,3 +1,2 @@
-/* Soft reset */
+/* Clear UART FIFOs */
 reg_write(serial, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, UART_FCR);
-reg_write(serial, 0x00, UART_OMAP_MDR1);